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Code Editor : adsp_dtbs.elf
ELF ��4 4 � � �� ���� �� � 8 8 CFGL $ $ p~ � " default_process-hamoa-1.0-adsp.dtb � x � " charger_process-hamoa-1.0-adsp.dtb � x � audio_process-hamoa-1.0-adsp.dtb �� x � ! sensor_process-hamoa-1.0-adsp.dtb � �� ~m 8 gt ( � g< qcom,hamoa root-process-hamoa-1.0-adsp soc , boot pinctrl@f100000 qcom,hamoa-pinctrl qcom,pinctrl 4 � 8 � ? E H P V f , qup0_se0_l0 r , ibi_i3c_qup0_se0_sda r , qup0_se0_l1 r , ibi_i3c_qup0_se0_scl r , qup0_se0_l2 r , qup0_se0_l3 r , qup0_se1_l0 r , qup0_se1_l1 r , qup0_se1_l2 r , qup0_se1_l3 r , qup0_se2_l0 r , qup0_se2_l1 r , qup0_se2_l2 r , qup0_se2_l3 r , qup0_se3_l0 r , qup0_se7_l2 r , qup0_se3_l1 r , qup0_se7_l3 r , qup0_se3_l2 r , qup0_se7_l0 r , qup0_se3_l3 r , qup0_se7_l1 r , qup0_se4_l0 r , qup0_se4_l1 r , qup0_se2_l4 r , qup0_se4_l2 r , qup0_se2_l5 r , qup0_se4_l3 r , qup0_se2_l6 r , qup0_se5_l0 r , qup0_se5_l1 r , ! qup0_se3_l6 r , " qup0_se5_l2 r , # qup0_se3_l5 r , $ qup0_se5_l3 r , % qup0_se3_l4 r , & qup0_se6_l0 r , ' qup0_se6_l1 r , ( qup0_se6_l2 r , ) qup0_se6_l3 r , * qup1_se0_l0 r , + ibi_i3c_qup1_se0_sda r , , qup1_se0_l1 r ! , - ibi_i3c_qup1_se0_scl r ! , . qup1_se3_l6 r ! , / qup1_se0_l2 r " , 0 qup1_se3_l5 r " , 1 qup1_se0_l3 r # , 2 qup1_se3_l4 r # , 3 qup1_se1_l0 r $ , 4 ibi_i3c_qup1_se1_sda r $ , 5 qup1_se1_l1 r % , 6 ibi_i3c_qup1_se1_scl r % , 7 qup1_se1_l2 r & , 8 qup1_se1_l3 r ' , 9 qup1_se2_l0 r ( , : qup1_se2_l1 r ) , ; qup1_se2_l2 r * , < qup1_se2_l3 r + , = qup1_se3_l0 r , , > qup1_se3_l1 r - , ? qup1_se3_l2 r . , @ qup1_se3_l3 r / , A qup1_se4_l0 r 0 , B qup1_se4_l1 r 1 , C qup1_se2_l4 r 1 , D qup1_se4_l2 r 2 , E qup1_se2_l5 r 2 , F qup1_se4_l3 r 3 , G qup1_se2_l6 r 3 , H qup1_se5_l0 r 4 , I qup1_se7_l2 r 4 , J qup1_se5_l1 r 5 , K qup1_se7_l3 r 5 , L qup1_se5_l2 r 6 , M qup1_se7_l0 r 6 , N qup1_se5_l3 r 7 , O qup1_se7_l1 r 7 , P qup1_se6_l0 r 8 , Q qup1_se6_l1 r 9 , R qup1_se6_l2 r : , S qup1_se6_l3 r ; , T qup2_se0_l0 r @ , U qup2_se0_l1 r A , V qup2_se3_l6 r A , W qup2_se0_l2 r B , X qup2_se3_l5 r B , Y qup2_se0_l3 r C , Z qup2_se3_l4 r C , [ qup2_se1_l0 r D , \ ibi_i3c_qup2_se1_sda r D , ] qup2_se1_l1 r E , ^ ibi_i3c_qup2_se1_scl r E , _ qup2_se1_l2 r F , ` qup2_se1_l3 r G , a qup2_se2_l0 r H , b qup2_se2_l1 r I , c qup2_se2_l2 r J , d qup2_se2_l3 r K , e qup2_se3_l0 r L , f qup2_se3_l1 r M , g qup2_se3_l2 r N , h qup2_se3_l3 r O , i qup2_se4_l0 r P , j qup2_se4_l1 r Q , k qup2_se2_l4 r Q , l qup2_se4_l2 r R , m qup2_se2_l5 r R , n qup2_se4_l3 r S , o qup2_se2_l6 r S , p qup2_se5_l0 r T , q qup2_se7_l2 r T , r qup2_se5_l1 r U , s qup2_se7_l3 r U , t qup2_se5_l2 r V , u qup2_se7_l0 r V , v qup2_se5_l3 r W , w qup2_se7_l1 r W , x qup2_se6_l0 r X , y qup2_se6_l1 r Y , z qup2_se6_l2 r Z , { qup2_se6_l3 r [ , | cci_i2c_sda0 r e , } cci_i2c_scl0 r f , ~ cci_i2c_sda1 r g , cci_i2c_scl1 r h , � cci_i2c_sda2 r i , � cci_i2c_scl2 r j , � qspi0_clk r , � qspi0_data_0 r � , � qspi0_data_1 r � , � qspi0_data_2 r � , � qspi0_data_3 r � , � qspi0_cs0_n r � , � qspi0_cs1_n r � , � aon_cci_i2c_sda3 r � , � aon_cci_i2c_scl3 r � , � pinctrl@6e80000 qcom,hamoa-pinctrl qcom,pinctrl 4� 8 ? E V f \ v E E E E E E E E E E E E E E E E E E E E E E E , � pinctrl@7a40000 qcom,hamoa-pinctrl qcom,pinctrl 4� � 8 � � ? E V f \ v a a a a Q Q E Q Q Q E E E E I E Q Q Q E a a Q , � ssc_qupv3_se0_0 r , � ssc_qupv3_se0_1 r , � ssc_qupv3_se1_0 r , � ssc_qupv3_se1_1 r , � ssc_qupv3_se2_0 r , � ssc_qupv3_se2_1 r , � ssc_qupv3_se2_2 r , � ssc_qupv3_se4_4 r , � ssc_gpio_0_clk r , � ssc_qupv3_se2_3 r , � ssc_qupv3_se4_5 r , � ssc_gpio_1_clk r , � ssc_qupv3_se3_0 r , � ssc_qupv3_se2_4 r , � ssc_gpio_2_clk r , � test_bus_lpi_cx_2 r , � test_bus_lpi_mx_2 r , � ssc_qupv3_se3_1 r , � ssc_gpio_3_clk r , � ssc_qupv3_se4_0 r , � ssc_gpio_4_clk r , � ssc_qupv3_se4_1 r , � ssc_gpio_5_clk r , � ssc_qupv3_se4_2 r , � ssc_gpio_6_clk r , � ssc_qupv3_se4_3 r , � ssc_gpio_7_clk r , � ssc_qupv3_se5_2 r , � ssc_gpio_8_clk r , � ssc_qupv3_se5_3 r , � ssc_gpio_9_clk r , � ssc_qupv3_se6_2 r , � ssc_qupv3_se6_0 r , � ssc_qupv3_se1_2 r , � ssc_gpio_10_clk r , � ssc_qupv3_se6_3 r , � ssc_qupv3_se6_1 r , � ssc_qupv3_se1_3 r , � ssc_gpio_11_clk r , � ssc_qupv3_se7_0 r , � ssc_qupv3_se7_1 r , � ssc_qupv3_se8_0 r , � ssc_qupv3_se8_1 r , � aon_cam_reset r , � sw , � core pmic battman charger_cfg qcom,pm-battman-charger jeita_cfg � ������� � � 7 7 � F F � b b � � � therm_thresh_cfg i n P U led_cfg % pl_chg_cfg 2 @2 Y�À p platform_cfg qcom,pm-battman-plat } � � � � :� � �� � ��w� � ! � - � < � M � ^ q z � � � �0 beh_cfg � � � � & 8 chg_table_cfg F � 6� R :� "� a �� �� o esd_cfg } :� � � � batt_auth_cfg � � � � � � , C+&D;^@��?c8Jb�� X offmode_cfg l � � � low_batt_shutdown_cfg � � � �< batt_recover_cfg �` 8 �� T � o � � power_key_cfg � < � - � � bcl_cfg 8� :� , >� A B usbpd_cfg qcom,pm-battman-usbpd ucsi_cap_cfg_uefi Z @F e n { � � 0 � ucsi_cap_cfg_hlos Z @F e n { � � � ucsi_conn_cap_cfg_uefi ���� � � � � � � � � ucsi_conn_cap_cfg_hlos ���� � � � � � � � � lpm_cfg_uefi lpm_cfg_hlos pd_policies_cfg_uefi 11 8 E6�, �, �, �, A, S S� f � y ���@ � � � � � �� ���@ � �6�, � , C X rp� r ���@ � rp� � � � � � � 2� � pd_policies_cfg_hlos 11 8 E6�, �, �, �, A, S S� f � y ���@ � � � � � �� ���@ � �6�, � , C X rp� r ���@ � �� � � � � � � 2� � lpd_cfg � � � � " < 2 � pd_static_info_cfg H � U 8 ^ � 8 tcpc_cfg_uefi n w ~ � � � � � � � � � � � � !!! tcpc_cfg_hlos n w ~ � � � � � � � � � � � � !!! vdm_cfg_uefi �@� ) 7 8 CG S c vdm_cfg_hlos �@� ) 7 8 CG Sa c psm_cfg q � � � rpm_cfg � � � a � � b gauge_cfg qcom,pm-battman-gauge � � &�� = , Q�� h w �d � ( � � < � d � � �$ � � � # 4 D � X c � power pld config qcom,power-pld pld_enable w pld_set_cap_bap_platform � pld_set_cap_bap_dtb � � �� d � pld_tunables � �)�' � �� � �e �)�' �� �e � , � > N M � __symbols__ /soc a/soc/pinctrl@f100000 ! f/soc/pinctrl@f100000/qup0_se0_l0 * r/soc/pinctrl@f100000/ibi_i3c_qup0_se0_sda ! �/soc/pinctrl@f100000/qup0_se0_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup0_se0_scl ! �/soc/pinctrl@f100000/qup0_se0_l2 ! �/soc/pinctrl@f100000/qup0_se0_l3 ! �/soc/pinctrl@f100000/qup0_se1_l0 ! �/soc/pinctrl@f100000/qup0_se1_l1 ! �/soc/pinctrl@f100000/qup0_se1_l2 ! �/soc/pinctrl@f100000/qup0_se1_l3 ! �/soc/pinctrl@f100000/qup0_se2_l0 ! �/soc/pinctrl@f100000/qup0_se2_l1 ! /soc/pinctrl@f100000/qup0_se2_l2 ! /soc/pinctrl@f100000/qup0_se2_l3 ! /soc/pinctrl@f100000/qup0_se3_l0 ! ,/soc/pinctrl@f100000/qup0_se7_l2 ! 8/soc/pinctrl@f100000/qup0_se3_l1 ! D/soc/pinctrl@f100000/qup0_se7_l3 ! P/soc/pinctrl@f100000/qup0_se3_l2 ! \/soc/pinctrl@f100000/qup0_se7_l0 ! h/soc/pinctrl@f100000/qup0_se3_l3 ! t/soc/pinctrl@f100000/qup0_se7_l1 ! �/soc/pinctrl@f100000/qup0_se4_l0 ! �/soc/pinctrl@f100000/qup0_se4_l1 ! �/soc/pinctrl@f100000/qup0_se2_l4 ! �/soc/pinctrl@f100000/qup0_se4_l2 ! �/soc/pinctrl@f100000/qup0_se2_l5 ! �/soc/pinctrl@f100000/qup0_se4_l3 ! �/soc/pinctrl@f100000/qup0_se2_l6 ! �/soc/pinctrl@f100000/qup0_se5_l0 ! �/soc/pinctrl@f100000/qup0_se5_l1 ! �/soc/pinctrl@f100000/qup0_se3_l6 ! �/soc/pinctrl@f100000/qup0_se5_l2 ! /soc/pinctrl@f100000/qup0_se3_l5 ! /soc/pinctrl@f100000/qup0_se5_l3 ! /soc/pinctrl@f100000/qup0_se3_l4 ! (/soc/pinctrl@f100000/qup0_se6_l0 ! 4/soc/pinctrl@f100000/qup0_se6_l1 ! @/soc/pinctrl@f100000/qup0_se6_l2 ! L/soc/pinctrl@f100000/qup0_se6_l3 ! X/soc/pinctrl@f100000/qup1_se0_l0 * d/soc/pinctrl@f100000/ibi_i3c_qup1_se0_sda ! y/soc/pinctrl@f100000/qup1_se0_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se0_scl ! �/soc/pinctrl@f100000/qup1_se3_l6 ! �/soc/pinctrl@f100000/qup1_se0_l2 ! �/soc/pinctrl@f100000/qup1_se3_l5 ! �/soc/pinctrl@f100000/qup1_se0_l3 ! �/soc/pinctrl@f100000/qup1_se3_l4 ! �/soc/pinctrl@f100000/qup1_se1_l0 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se1_sda ! �/soc/pinctrl@f100000/qup1_se1_l1 * /soc/pinctrl@f100000/ibi_i3c_qup1_se1_scl ! /soc/pinctrl@f100000/qup1_se1_l2 ! $/soc/pinctrl@f100000/qup1_se1_l3 ! 0/soc/pinctrl@f100000/qup1_se2_l0 ! </soc/pinctrl@f100000/qup1_se2_l1 ! H/soc/pinctrl@f100000/qup1_se2_l2 ! T/soc/pinctrl@f100000/qup1_se2_l3 ! `/soc/pinctrl@f100000/qup1_se3_l0 ! l/soc/pinctrl@f100000/qup1_se3_l1 ! x/soc/pinctrl@f100000/qup1_se3_l2 ! �/soc/pinctrl@f100000/qup1_se3_l3 ! �/soc/pinctrl@f100000/qup1_se4_l0 ! �/soc/pinctrl@f100000/qup1_se4_l1 ! �/soc/pinctrl@f100000/qup1_se2_l4 ! �/soc/pinctrl@f100000/qup1_se4_l2 ! �/soc/pinctrl@f100000/qup1_se2_l5 ! �/soc/pinctrl@f100000/qup1_se4_l3 ! �/soc/pinctrl@f100000/qup1_se2_l6 ! �/soc/pinctrl@f100000/qup1_se5_l0 ! �/soc/pinctrl@f100000/qup1_se7_l2 ! �/soc/pinctrl@f100000/qup1_se5_l1 ! /soc/pinctrl@f100000/qup1_se7_l3 ! /soc/pinctrl@f100000/qup1_se5_l2 ! /soc/pinctrl@f100000/qup1_se7_l0 ! ,/soc/pinctrl@f100000/qup1_se5_l3 ! 8/soc/pinctrl@f100000/qup1_se7_l1 ! D/soc/pinctrl@f100000/qup1_se6_l0 ! P/soc/pinctrl@f100000/qup1_se6_l1 ! \/soc/pinctrl@f100000/qup1_se6_l2 ! h/soc/pinctrl@f100000/qup1_se6_l3 ! t/soc/pinctrl@f100000/qup2_se0_l0 ! �/soc/pinctrl@f100000/qup2_se0_l1 ! �/soc/pinctrl@f100000/qup2_se3_l6 ! �/soc/pinctrl@f100000/qup2_se0_l2 ! �/soc/pinctrl@f100000/qup2_se3_l5 ! �/soc/pinctrl@f100000/qup2_se0_l3 ! �/soc/pinctrl@f100000/qup2_se3_l4 ! �/soc/pinctrl@f100000/qup2_se1_l0 * �/soc/pinctrl@f100000/ibi_i3c_qup2_se1_sda ! �/soc/pinctrl@f100000/qup2_se1_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup2_se1_scl ! /soc/pinctrl@f100000/qup2_se1_l2 ! /soc/pinctrl@f100000/qup2_se1_l3 ! "/soc/pinctrl@f100000/qup2_se2_l0 ! ./soc/pinctrl@f100000/qup2_se2_l1 ! :/soc/pinctrl@f100000/qup2_se2_l2 ! F/soc/pinctrl@f100000/qup2_se2_l3 ! R/soc/pinctrl@f100000/qup2_se3_l0 ! ^/soc/pinctrl@f100000/qup2_se3_l1 ! j/soc/pinctrl@f100000/qup2_se3_l2 ! v/soc/pinctrl@f100000/qup2_se3_l3 ! �/soc/pinctrl@f100000/qup2_se4_l0 ! �/soc/pinctrl@f100000/qup2_se4_l1 ! �/soc/pinctrl@f100000/qup2_se2_l4 ! �/soc/pinctrl@f100000/qup2_se4_l2 ! �/soc/pinctrl@f100000/qup2_se2_l5 ! �/soc/pinctrl@f100000/qup2_se4_l3 ! �/soc/pinctrl@f100000/qup2_se2_l6 ! �/soc/pinctrl@f100000/qup2_se5_l0 ! �/soc/pinctrl@f100000/qup2_se7_l2 ! �/soc/pinctrl@f100000/qup2_se5_l1 ! �/soc/pinctrl@f100000/qup2_se7_l3 ! /soc/pinctrl@f100000/qup2_se5_l2 ! /soc/pinctrl@f100000/qup2_se7_l0 ! /soc/pinctrl@f100000/qup2_se5_l3 ! */soc/pinctrl@f100000/qup2_se7_l1 ! 6/soc/pinctrl@f100000/qup2_se6_l0 ! B/soc/pinctrl@f100000/qup2_se6_l1 ! N/soc/pinctrl@f100000/qup2_se6_l2 ! Z/soc/pinctrl@f100000/qup2_se6_l3 " f/soc/pinctrl@f100000/cci_i2c_sda0 " s/soc/pinctrl@f100000/cci_i2c_scl0 " �/soc/pinctrl@f100000/cci_i2c_sda1 " �/soc/pinctrl@f100000/cci_i2c_scl1 " �/soc/pinctrl@f100000/cci_i2c_sda2 " �/soc/pinctrl@f100000/cci_i2c_scl2 �/soc/pinctrl@f100000/qspi0_clk " �/soc/pinctrl@f100000/qspi0_data_0 " �/soc/pinctrl@f100000/qspi0_data_1 " �/soc/pinctrl@f100000/qspi0_data_2 " �/soc/pinctrl@f100000/qspi0_data_3 ! �/soc/pinctrl@f100000/qspi0_cs0_n ! �/soc/pinctrl@f100000/qspi0_cs1_n & /soc/pinctrl@f100000/aon_cci_i2c_sda3 & /soc/pinctrl@f100000/aon_cci_i2c_scl3 ,/soc/pinctrl@6e80000 5/soc/pinctrl@7a40000 % >/soc/pinctrl@7a40000/ssc_qupv3_se0_0 % N/soc/pinctrl@7a40000/ssc_qupv3_se0_1 % ^/soc/pinctrl@7a40000/ssc_qupv3_se1_0 % n/soc/pinctrl@7a40000/ssc_qupv3_se1_1 % ~/soc/pinctrl@7a40000/ssc_qupv3_se2_0 % �/soc/pinctrl@7a40000/ssc_qupv3_se2_1 % �/soc/pinctrl@7a40000/ssc_qupv3_se2_2 % �/soc/pinctrl@7a40000/ssc_qupv3_se4_4 $ �/soc/pinctrl@7a40000/ssc_gpio_0_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se2_3 % �/soc/pinctrl@7a40000/ssc_qupv3_se4_5 $ �/soc/pinctrl@7a40000/ssc_gpio_1_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se3_0 % /soc/pinctrl@7a40000/ssc_qupv3_se2_4 $ /soc/pinctrl@7a40000/ssc_gpio_2_clk ' +/soc/pinctrl@7a40000/test_bus_lpi_cx_2 ' =/soc/pinctrl@7a40000/test_bus_lpi_mx_2 % O/soc/pinctrl@7a40000/ssc_qupv3_se3_1 $ _/soc/pinctrl@7a40000/ssc_gpio_3_clk % n/soc/pinctrl@7a40000/ssc_qupv3_se4_0 $ ~/soc/pinctrl@7a40000/ssc_gpio_4_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se4_1 $ �/soc/pinctrl@7a40000/ssc_gpio_5_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se4_2 $ �/soc/pinctrl@7a40000/ssc_gpio_6_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se4_3 $ �/soc/pinctrl@7a40000/ssc_gpio_7_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se5_2 $ �/soc/pinctrl@7a40000/ssc_gpio_8_clk % /soc/pinctrl@7a40000/ssc_qupv3_se5_3 $ /soc/pinctrl@7a40000/ssc_gpio_9_clk % (/soc/pinctrl@7a40000/ssc_qupv3_se6_2 % 8/soc/pinctrl@7a40000/ssc_qupv3_se6_0 % H/soc/pinctrl@7a40000/ssc_qupv3_se1_2 % X/soc/pinctrl@7a40000/ssc_gpio_10_clk % h/soc/pinctrl@7a40000/ssc_qupv3_se6_3 % x/soc/pinctrl@7a40000/ssc_qupv3_se6_1 % �/soc/pinctrl@7a40000/ssc_qupv3_se1_3 % �/soc/pinctrl@7a40000/ssc_gpio_11_clk % �/soc/pinctrl@7a40000/ssc_qupv3_se7_0 % �/soc/pinctrl@7a40000/ssc_qupv3_se7_1 % �/soc/pinctrl@7a40000/ssc_qupv3_se8_0 % �/soc/pinctrl@7a40000/ssc_qupv3_se8_1 # �/soc/pinctrl@7a40000/aon_cam_reset �/sw model compatible #address-cells #size-cells phandle reg ngpios width id version egpio gpio-controller #gpio-cells mux qcom,sleep-config gpio-mapping jeita-alg afp-cold-degc jeita-hard-cold-degc jeita-hard-hot-degc afp-hot-degc vflt-nominal-mv fcc-nominal-ma die-temp-cfg conn-temp-cfg chg-led done-chg-led en-pl-chg-opt pl-chg-slave-max-pwr-pct en-pl-chg-adptr-pwr-uw pl-chg-index struct-ver plat-id is-test-mode test-mode-flag chg-heartbeat-timer-ms dischg-heartbeat-timer-ms poll-timer-ms chg-done-timer-ms vbatt-avg-sample-size en-linear-soc soc-conv-pt min-linear-soc wd-bark-timer-ms wd-bite-timer-ms gen-test-interface iterm-ma en-btp en-bmd charger-port-num charger-index-table pre-chg-done-timer-min en-beh beh-debug-board beh-normal-batt beh-smart-auth-state beh-unknown-state beh-batt-miss-state beh-invalid-state beh-afp-state dbg-rid-cfg normal-rid-cfg smart-rid-cfg chg-table-max esd-timer-ms esd-voltage-mv esd-init-soc en-batt-auth batt-auth-timeout-s batt-auth-checktimer-ms batt-unauth-charging-action batt-auth-public-key-len batt-auth-challenge-len batt-auth-response-len batt-auth-public-key batt-auth-algorithm off-mode-src-soc-thr off-mode-src-vbat-thd-delta-mv off-mode-eoc-usbin-mv low-batt-shutdown-feature-en low-batt-soc-thr critical-batt-soc-thr wdog-bite-timer-s en-batt-recover batt-recover-i2c-timeout-ms batt-recover-fet-timeout-ms batt-recover-checktimer-ms batt-recover-current-ma batt-recover-en-sysov boot-min-power-missing-batt-w boot-min-power-missing-batt-2s-w boot-min-power-dead-batt-w boot-min-soc ibatt-high-chg-ma ibatt-too-high-chg-ma ibatt-high-dischg-ma ibatt-too-high-dischg-ma attributes conn-num num-alt-mode bc-ver pd-ver typec-ver bm-optional-features op-mode provider consumer dfp-swap-en ufp-swap-en src-swap-en snk-swap-en ext-op-mode misc-cap port-idx en-pd en-pan en-legacy-cable-det pd-rev snk-cap-size snk-caps-pdos snk-max-voltage-mv snk-max-current-ma snk-pwr-eval-alg snk-max-pwr-uw src-max-voltage-mv src-max-current-ma src-max-pwr-uw sys-power-budget src-cap-size src-caps-pdos en-pps en-vconn-swap en-fr-swap en-vdm-dp-altmode en-vdm-cable-discovery en-vdm-tbt3-alt-mode tbt3-min-operating-pwr-uw en-enterprise-mgmt slow-charge-thr mismatch-thr drp-pps-support mpm-snk-time-ms mpm-src-time-ms pan-ack-tmout-ms preferred-role-cfg en-lpd en-fod rsbu-thr-kohm holdoff-time-ms cooldown-time-s mitigation-current-ma batt-cap-vid batt-pid src-cap-ext-cfg pmic-idx en-snk en-src dam-en en-dam-src src-rp-val en-port-cfg-ovr en-audio-adap vbus-rampdown-wait-ms vbus-default-mv vbus-init-step-mv en-vbus-ocp-support drp-duty-cycle id-header-vdo cert-stat-vdo product-vdo dfp-product-vdo ufp-product-vdo resp-disc-sop power-key-timeout-ms power-state-to-led en-ext-alert-type rpm_access_mode rpm_intrx_gpio_cfg rpm_intrx_gpio_idx rpm_inttx_gpio_cfg rpm_inttx_gpio_idx vph-min-mv fvss-entry-delta-mv fvss-vbatt-filt-tau-us fcss-entry-delta-ma fcss-ibatt-filt-tau-us hold-soc-1-pct cl-learn-min-delta-soc cl-wt-learn soh-tbat-range-degc soh-soc-range ignore-shdn-soc-param pon-debug-fifo-count hpm-fifo-len vbatt-empty-1s vbatt-empty-2s en-split-profile seperate-2p-batt vbat-cut-off-mv ibatt-cutoff-min-ma rconn-mohm ibatt-full-delta-ma pld-en-pld-cfg pld-en-platform-en pld-en-dtb-cap-bap-bwd pld-default-cap-bap-bwd pld-en-tunables pld-cap-kp pld-cap-ki pld-cap-kd pld-bap-kp pld-bap-ki pld-bap-kd pld-cap-ki-period pld-bap-ki-period pld-ewma-alpha pld-reset-ewma-time tlmm qup0_se0_l0 ibi_i3c_qup0_se0_sda qup0_se0_l1 ibi_i3c_qup0_se0_scl qup0_se0_l2 qup0_se0_l3 qup0_se1_l0 qup0_se1_l1 qup0_se1_l2 qup0_se1_l3 qup0_se2_l0 qup0_se2_l1 qup0_se2_l2 qup0_se2_l3 qup0_se3_l0 qup0_se7_l2 qup0_se3_l1 qup0_se7_l3 qup0_se3_l2 qup0_se7_l0 qup0_se3_l3 qup0_se7_l1 qup0_se4_l0 qup0_se4_l1 qup0_se2_l4 qup0_se4_l2 qup0_se2_l5 qup0_se4_l3 qup0_se2_l6 qup0_se5_l0 qup0_se5_l1 qup0_se3_l6 qup0_se5_l2 qup0_se3_l5 qup0_se5_l3 qup0_se3_l4 qup0_se6_l0 qup0_se6_l1 qup0_se6_l2 qup0_se6_l3 qup1_se0_l0 ibi_i3c_qup1_se0_sda qup1_se0_l1 ibi_i3c_qup1_se0_scl qup1_se3_l6 qup1_se0_l2 qup1_se3_l5 qup1_se0_l3 qup1_se3_l4 qup1_se1_l0 ibi_i3c_qup1_se1_sda qup1_se1_l1 ibi_i3c_qup1_se1_scl qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se4_l0 qup1_se4_l1 qup1_se2_l4 qup1_se4_l2 qup1_se2_l5 qup1_se4_l3 qup1_se2_l6 qup1_se5_l0 qup1_se7_l2 qup1_se5_l1 qup1_se7_l3 qup1_se5_l2 qup1_se7_l0 qup1_se5_l3 qup1_se7_l1 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup2_se0_l0 qup2_se0_l1 qup2_se3_l6 qup2_se0_l2 qup2_se3_l5 qup2_se0_l3 qup2_se3_l4 qup2_se1_l0 ibi_i3c_qup2_se1_sda qup2_se1_l1 ibi_i3c_qup2_se1_scl qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 qup2_se2_l1 qup2_se2_l2 qup2_se2_l3 qup2_se3_l0 qup2_se3_l1 qup2_se3_l2 qup2_se3_l3 qup2_se4_l0 qup2_se4_l1 qup2_se2_l4 qup2_se4_l2 qup2_se2_l5 qup2_se4_l3 qup2_se2_l6 qup2_se5_l0 qup2_se7_l2 qup2_se5_l1 qup2_se7_l3 qup2_se5_l2 qup2_se7_l0 qup2_se5_l3 qup2_se7_l1 qup2_se6_l0 qup2_se6_l1 qup2_se6_l2 qup2_se6_l3 cci_i2c_sda0 cci_i2c_scl0 cci_i2c_sda1 cci_i2c_scl1 cci_i2c_sda2 cci_i2c_scl2 qspi0_clk qspi0_data_0 qspi0_data_1 qspi0_data_2 qspi0_data_3 qspi0_cs0_n qspi0_cs1_n aon_cci_i2c_sda3 aon_cci_i2c_scl3 lpi_tlmm ssc_tlmm ssc_qupv3_se0_0 ssc_qupv3_se0_1 ssc_qupv3_se1_0 ssc_qupv3_se1_1 ssc_qupv3_se2_0 ssc_qupv3_se2_1 ssc_qupv3_se2_2 ssc_qupv3_se4_4 ssc_gpio_0_clk ssc_qupv3_se2_3 ssc_qupv3_se4_5 ssc_gpio_1_clk ssc_qupv3_se3_0 ssc_qupv3_se2_4 ssc_gpio_2_clk test_bus_lpi_cx_2 test_bus_lpi_mx_2 ssc_qupv3_se3_1 ssc_gpio_3_clk ssc_qupv3_se4_0 ssc_gpio_4_clk ssc_qupv3_se4_1 ssc_gpio_5_clk ssc_qupv3_se4_2 ssc_gpio_6_clk ssc_qupv3_se4_3 ssc_gpio_7_clk ssc_qupv3_se5_2 ssc_gpio_8_clk ssc_qupv3_se5_3 ssc_gpio_9_clk ssc_qupv3_se6_2 ssc_qupv3_se6_0 ssc_qupv3_se1_2 ssc_gpio_10_clk ssc_qupv3_se6_3 ssc_qupv3_se6_1 ssc_qupv3_se1_3 ssc_gpio_11_clk ssc_qupv3_se7_0 ssc_qupv3_se7_1 ssc_qupv3_se8_0 ssc_qupv3_se8_1 aon_cam_reset sw � �� w 8 < ( ; qcom,hamoa charger-process-hamoa-1.0-adsp soc , sw , __symbols__ 4/soc 8/sw model compatible #address-cells #size-cells phandle soc sw � �� w 8 < ( ; qcom,hamoa audio-process-hamoa-1.0-adsp soc , sw , __symbols__ 4/soc 8/sw model compatible #address-cells #size-cells phandle soc sw � �� w 8 < ( ; qcom,hamoa sensor-process-hamoa-1.0-adsp soc , sw , __symbols__ 4/soc 8/sw model compatible #address-cells #size-cells phandle soc sw � � h S � @ VZ b߾g��D�{E��C3 <&a�B�WT��rgߝ��z� ,>= �Q}�#��VY�2��),J�_�X�I�O�B�1�c��v��!m�� ~Kڌ 0d0S䊽]��7� ��D.'���ꥼ+�Ǫ�f aH���k��Y��QI��0vםZ���0B���3B�V;����Z�E�Hjq1qy ���%͖�T���.Cl 0�M0�Ӡ � � 1�h~0 *�H�=0l1 0 UCN1&0$U Lenovo Product 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